Design of a Delay Locked Loop
A DLL is a digital circuit used to change the phase of the clocked signal (a signal with periodic waveform) while keeping the frequency unchanged.A DLL is a digital circuit used to change the phase of the clocked signal (a signal with periodic waveform) while keeping the frequency unchanged.
A DLL compares the phase of its last output with the input clock to generate an error signal which is then integrated and fed back as the control to all of the delay elements. The integration allows the error to go to zero while keeping the control signal, and thus the delays, where they need to be for phase lock. Since the control signal directly impacts the phase this is all that is required.
Clock and data recovery
In many systems, data is transmitted or retrieved without any additional timing reference. For example, in optical communications, a stream of data flows over a single fiber with no accompanying clock, but the receiver is required to synchronously. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a DLL. This process is commonly known as clock and data recovery (CDR).
CDR: This type of CDR uses a PLL or DLL to implement a reference loop which accepts an input reference clock signal and produces a set of high speed clock signals, used as reference phases, spaced evenly across 360 degrees. These reference phases are then fed to a CDR loop which includes circuitry for selecting pairs of reference phases and interpolating between them to provide clocks for recovering the data from the data signal
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